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CY7C1069AV33
2M x 8 Static RAM
Features
* High speed -- tAA = 8, 10, 12 ns * Low active power -- 1080 mW (max.) * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1 and CE2 features device is accomplished by enabling the chip (by taking CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Reading from the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) as well as forcing the Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1069AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-ball fine-pitch ball grid array (FBGA) package.
Functional Description
The CY7C1069AV33 is a high-performance CMOS Static RAM organized as 2,097,152 words by 8 bits. Writing to the
Logic Block Diagram
Pin Configuration
TSOP II Top View
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
2M x 8 ARRAY 4096 x 4096
I/O0-I/O7
COLUMN DECODER
WE CE2 OE CE1
NC VCC NC I/O6 VSS I/O7 A4 A3 A2 A1 A0 NC CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 NC VSS NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
NC VSS NC I/O5 VCC I/O4 A5 A6 A7 A8 A9 NC OE VSS DNU A20 A10 A11 A12 A13 A14 I/O3 VSS I/O2 NC
ROW DECODER
A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 A20
SENSE AMPS
VCC
NC
Selection Guide
-8 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/Industrial 8 300 300 50 -10 10 275 275 50 -12 12 260 260 50 mA Unit ns mA
Cypress Semiconductor Corporation Document #: 38-05255 Rev. *D
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 10, 2003
CY7C1069AV33
Pin Configurations
48-ball FBGA 1 NC NC I/O 0 2 OE NC NC (Top View) 4 3 A0 A3 A5 A1 A4 A6 A 7 5 A2 CE1 NC 6 CE2 NC I/O 4 A B C D E F G H
VSS I/O1 A17 V CC I/O 2 I/O 3 NC A19 NC A18 A14
I/O 5 V CC VSS I/O 7
A16 I/O 6 A15 A13 A10 NC
DNU A 12 A8 A9
WE NC A11 A20
Document #: 38-05255 Rev. *D
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CY7C1069AV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................-0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current GND < VI < VCC Output Leakage Current GND < VOUT < VCC, Output Disabled VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs VCC = Max., f = fMAX Commercial = 1/tRC Industrial CE2 < VIL, Max. VCC, SCE > VIH VIN > VIH or VIN < VIL, f = fMAX CE2 < 0.3V Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Commercial/ Industrial Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 0.3V
-8 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 300 300 70 2.0 Max. 2.4
-10 Min. Max. 2.4 0.4 VCC + 0.3 0.8 +1 +1 275 275 70 2.0
-12 Min. Max. Unit V 0.4 VCC + 0.3 0.8 +1 +1 260 260 70 V V V A A mA mA mA
-0.3 -1 -1
-0.3 -1 -1
ISB2
50
50
50
mA
Capacitance[2]
Parameter CIN COUT Package Z54 BA48 Z54 BA48
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters.
Description Input Capacitance I/O Capacitance
Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V
Max. 6 8 8 10
Unit pF pF pF pF
Document #: 38-05255 Rev. *D
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CY7C1069AV33
AC Test Loads and Waveforms[3]
50 OUTPUT Z0 = 50 (a) 3.3V *Capacitive Load consists of all components of the test environment GND Rise time > 1V/ns 30 pF* All input pulses 90% 10% (c) 90% 10% (b) VTH = 1.5V 3.3V OUTPUT 5 pF* R2 351 *Including jig and scope R1 317
Fall time: > 1V/ns
[4]
AC Switching Characteristics Over the Operating Range
Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Cycle[8, 9] Write Cycle Time CE1 LOW/CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[6] WE LOW to High-Z[6] 8 6 6 0 0 6 5 0 3 VCC(typical) to the First Access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW/CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z[6]
[6]
-8 Description Min. 1 8 10 3 8 5 1 5 3 5 0 8 10 7 7 0 0 7 5.5 0 3 5 0 3 1 3 Max. Min. 1 10
-10 Max. Min. 1 12 10 3 10 5 1 5 3 5 0 10 12 8 8 0 0 8 6 0 3 5
-12 Max. Unit ms ns 12 12 6 6 6 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 ns
OE HIGH to High-Z[6] CE1 LOW/CE2 HIGH to Low-Z CE1 LOW/CE2 HIGH to CE1 HIGH/CE2 LOW to High-Z[6] Power-up[7] CE1 HIGH/CE2 LOW to Power-down[7]
Notes: 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD , normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 5. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is started. 6. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal Write time of the memory is defined by the overlap of CE1 LOW / CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05255 Rev. *D
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CY7C1069AV33
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled) [11, 12]
ADDRESS tRC CE1
CE2 tASCE OE tDOE tLZOE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZSCE tPU 50% DATA VALID tPD 50% ISB ICC tHZOE tHZSCE HIGH IMPEDANCE
Notes: 10. Device is continuously selected. CE1 = VIL, CE2 = VIH. 11. WE is HIGH for Read cycle.
Document #: 38-05255 Rev. *D
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CY7C1069AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 Controlled)[13, 14, 15]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE t BW tSD DATAI/O tHD
tHA
Write Cycle No. 2 (WE Controlled, OE LOW) [13, 14, 15]
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tHZWE DATA I/O tLZWE tSD tHD
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0-I/O7 High-Z High-Z Data Out Data In High-Z Power-down Power-down Read All Bits Write All Bits Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Notes: 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 13. Data I/O is high-impedance if OE = VIH. 14. If CE1 goes HIGH / CE2 LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. CE above is defined as a combination of CE1 and CE2. It is active low.
Document #: 38-05255 Rev. *D
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CY7C1069AV33
Ordering Information
Speed (ns) 8 Ordering Code[16] CY7C1069AV33-8ZC CY7C1069AV33-8ZI CY7C1069AV33-8BAC CY7C1069AV33-8BAI CY7C1069AV33-10ZC CY7C1069AV33-10ZI CY7C1069AV33-10BAC CY7C1069AV33-10BAI CY7C1069AV33-12ZC CY7C1069AV33-12ZI CY7C1069AV33-12BAC CY7C1069AV33-12BAI Package Name Z54 BA48 Z54 BA48 Z54 BA48 Package Type 54-pin TSOP II 48-ball Mini BGA 54-pin TSOP II 48-ball Mini BGA 54-pin TSOP II 48-ball Mini BGA Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
10
12
Package Diagrams
54-lead Thin Small Outline Package, Type II Z54-II
51-85160-**
Note: 16. Contact a Cypress Representative for availability of the 48-ball Mini BGA (BA48) package.
Document #: 38-05255 Rev. *D
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CY7C1069AV33
Package Diagrams (continued)
48-ball (8 mm x 20 mm x 1.2 mm) FBGA BA48G
51-85162-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05255 Rev. *D
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1069AV33
Document History Page
Document Title: CY7C1069AV33 2M x 8 Static RAM Document Number: 38-05255 REV. ** *A *B ECN NO. 113724 117060 117990 Issue Date 03/27/02 07/31/02 08/30/02 Orig. of Change NSL DFP DFP New Data Sheet Removed 15-ns bin Added 8-ns bin Changing ICC for 8, 10, 12 bins tpower changed from 1 s to 1 ms Load Cap Comment changed (for Tx line load) tSD changed to 5.5 ns for the 10-ns bin Changed some 8-ns bin #'s (tHZ, tDOE, tDBE) Removed hz < lz comments Final Data Sheet Added note 4 to "AC Test Loads and Waveforms" and note 7 to tpu and tpd Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin TSOP to 6/8 pf Changed ISB1 from 100 mA to 70 mA Shaded the 48fBGA product offering information Description of Change
*C
120385
11/13/02
DFP
*D
124441
2/25/03
MEG
Document #: 38-05255 Rev. *D
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